Conventionally, a surface mounting technology of mounting an electronic component such as a chip-type multilayer ceramic capacitor on a substrate has been widely known. Such a surface mounting technology includes a technology researched and developed to achieve a fuse function to prevent, for example, burnout and firing of the mounting substrate when large current flows through the mounted electronic component.
For example, Patent Document 1 discloses a mounting device for a surface-mounted component as illustrated in FIG. 11.
This mounting device includes a surface-mounted wiring board 101, first land electrodes 102a and 102b provided on an upper surface of the surface-mounted wiring board 101, an intermediate connection layer 105, on upper and lower surfaces of which second land electrodes 103a and 103b and third land electrodes 104a and 104b are respectively provided, and a surface-mounted component 106. The first land electrodes 102a and 102b are electrically connected with the third land electrodes 104a and 104b through solder 107a and 107b, respectively, and the second land electrodes 103a and 103b are electrically connected with external electrodes 108a and 108b of the surface-mounted component 106, respectively, through solder 109a and 109b. 
FIG. 12 is a view in the direction indicated by arrows X-X in FIG. 11.
Specifically, in the device disclosed in Patent Document 1, the intermediate connection layer 105 includes a conducting via 110 electrically connecting the second land electrode 103b and the third land electrode 104b, and the first land electrode 102b of the surface-mounted wiring board 101 is electrically connected with the external electrode 108b of the surface-mounted component 106 through the conducting via 110. In the device disclosed in Patent Document 1, a conductive pattern 111 having a thin line structure including a fuse 111a is formed on the intermediate connection layer 105 and suspended at an one end part 105a, and the second land electrode 103a is electrically connected with the third land electrode 104a through the conductive pattern 111, and accordingly, the land electrode 102a of the surface-mounted wiring board 101 is electrically connected with the external electrode 108a of the surface-mounted component 106.
In the device disclosed in Patent Document 1, since an intermediate connection layer having a fuse function is interposed between an electronic component and a mounting substrate, the fuse function achieves an open circuit when large current equal to or larger than rated current flows through the mounted electronic component and damages the electronic component, and accordingly, influence on any peripheral mounting component is minimized to prevent, for example, burnout and firing of the mounting substrate.
Patent Document 2 discloses a circuit board as illustrated in FIG. 13.
In the circuit board disclosed in Patent Document 2, a circuit protecting device 111 includes breaking parts 114a and 115a configured to prevent conduction of conductor end parts 114 and 115 of a conductor pattern 113 formed on a principal surface of a circuit board 112 made of an insulation resin material such as glass epoxy resin, and a conductor member 116 is bridged between the conductor end parts 114 and 115.
FIG. 14 is a cross-sectional view in the direction indicated by arrows Y-Y in FIG. 13.
In the circuit board disclosed in Patent Document 2, soldering paste is applied on the conductor end parts 114 and 115 to form a solder part 118, and soldering paste having a melting point higher than that for the solder part 118 is applied to form the conductor member 116 having a fuse function.
In the circuit board disclosed in Patent Document 2, for example, when eddy current flows through an earth wire, heat is generated at the conductor pattern 113, the solder part 118, and the conductor member 116 and melts the conductor member 116 to allow the soldering paste of the conductor member 116 to flow into a hole 117. This opens the conductor end parts 114 and 115 and puts a circuit in a non-conduction state, and accordingly, prevents damage on the circuit due to the eddy current flowing thereto.
Patent Document 1: Japanese Patent Application Laid-open No. 8-18285 (claims 4 and 5, paragraphs [0011] and [0014], and FIGS. 1 and 6, for example)
Patent Document 2: Japanese Patent Application Laid-open No. 2010-73805 (claim 1, paragraphs [0012] to [0022], and FIG. 2, for example)